玩命加载中 . . .

SpinalHDL基础-算术与移位运算

SpinalHDL

无符号数——运算

class top extends Module{
    val a = UInt(5 bits)
    val b = UInt(8 bits)
    
    val res1 = a + b + 1
    val res2 = a - b - 1
    val res3 = a * b
}

module top (
);

  wire       [4:0]    a;
  wire       [7:0]    b;
  wire       [7:0]    res1;
  wire       [7:0]    res2;
  wire       [12:0]   res3;

  assign res1 = (({3'd0, a} + b) + 8'h01);
  assign res2 = (({3'd0, a} - b) - 8'h01);
  assign res3 = (a * b);

endmodule

无符号数——常数移位

class top extends Module{
    val a = UInt(8 bits)
    
    val res1 = a >> 2    //n-2 bits
    val res2 = a << 2    //n+2 bits
    val res3 = a |>> 2   //n bits
    val res4 = a |<< 2   //n bits
}

module top (
);

  wire       [7:0]    a;
  wire       [5:0]    res1;
  wire       [9:0]    res2;
  wire       [7:0]    res3;
  wire       [7:0]    res4;

  assign res1 = (a >>> 2);
  assign res2 = ({2'd0,a} <<< 2);
  assign res3 = (a >>> 2);
  assign res4 = (a <<< 2);

endmodule

无符号数——变量移位

class top extends Module{
    val a = UInt(8 bits)
    val shift_bit = UInt(2 bits)
    
    val res1 = a >>  shift_bit    //n bits
    val res2 = a <<  shift_bit    //n+max(shift) bits
    val res3 = a |>> shift_bit    //n bits
    val res4 = a |<< shift_bit    //n bits
}

module top (
);

  wire       [7:0]    a;
  wire       [1:0]    shift_bit;
  wire       [7:0]    res1;
  wire       [10:0]   res2;
  wire       [7:0]    res3;
  wire       [7:0]    res4;

  assign res1 = (a >>> shift_bit);
  assign res2 = ({3'd0,a} <<< shift_bit);
  assign res3 = (a >>> shift_bit);
  assign res4 = (a <<< shift_bit);

endmodule

有符号数——运算

class top extends Module{
    val a = SInt(5 bits)
    val b = SInt(8 bits)
    
    val res1 = a + b + 1
    val res2 = a - b - 1
    val res3 = a * b
}

module top (
);

  wire       [4:0]    a;
  wire       [7:0]    b;
  wire       [7:0]    res1;
  wire       [7:0]    res2;
  wire       [12:0]   res3;

  assign res1 = (({ {3{a[4]}}, a} + b) + 8'h01);
  assign res2 = (({ {3{a[4]}}, a} - b) - 8'h01);
  assign res3 = ($signed(a) * $signed(b));

endmodule

有符号数——常数移位

class top extends Module{
    val a = SInt(8 bits)
    
    val res1 = a >> 2    //n-2 bits
    val res2 = a << 2    //n+2 bits
    val res3 = a |>> 2   //n bits
    val res4 = a |<< 2   //n bits
}

module top (
);

  wire       [7:0]    a;
  wire       [5:0]    res1;
  wire       [9:0]    res2;
  wire       [7:0]    res3;
  wire       [7:0]    res4;

  assign res1 = (a >>> 2);
  assign res2 = ({2'd0,a} <<< 2);
  assign res3 = ($signed(a) >>> 2);
  assign res4 = (a <<< 2);

endmodule

有符号数——变量移位

class top extends Module{
    val a = SInt(8 bits)
    val shift_bit = UInt(2 bits)
    
    val res1 = a >>  shift_bit    //n bits
    val res2 = a <<  shift_bit    //n+max(shift) bits
    val res3 = a |>> shift_bit    //n bits
    val res4 = a |<< shift_bit    //n bits
}

module top (
);

  wire       [7:0]    a;
  wire       [1:0]    shift_bit;
  wire       [7:0]    res1;
  wire       [10:0]   res2;
  wire       [7:0]    res3;
  wire       [7:0]    res4;

  assign res1 = ($signed(a) >>> shift_bit);
  assign res2 = ({ {3{a[7]}},a} <<< shift_bit);
  assign res3 = ($signed(a) >>> shift_bit);
  assign res4 = ($signed(a) <<< shift_bit);

endmodule

本文作者： 董续胜

本文链接： https://dxsm.github.io/p/spinalhdl-algorithm.html

版权声明： 本博客所有文章除特别声明外，均采用CC BY-NC-SA 3.0许可协议。转载请注明出处！

 上一页

SpinalHDL

 评论