SpinalHDL基础-状态机枚举

Enum

• SpinalHDL
• Verilog

class top extends Module{
    val io = new Bundle {
        val start = in Bool()
    }
    
    object mainState extends SpinalEnum {
        val IDLE,TX_DATA,DONE = newElement()
        rawElementName()  //状态机名去掉object名字前缀
    }
    val cstate = mainState() setAsReg() init(mainState.IDLE)
    val nstate = mainState()
    
    val cnt = Reg(UInt(5 bits)) init(0)
    when(io.start) {
        cnt := 0
    } elsewhen(cstate === mainState.TX_DATA) {
        cnt := cnt + 1
    }
    
    cstate := nstate
    switch(cstate) {
        is(mainState.IDLE) {
            when(io.start) {
                nstate := mainState.TX_DATA
            } otherwise {
                nstate := cstate
            }
        }
        is(mainState.TX_DATA) {
            when(cnt === U"5'd31") {
                nstate := mainState.DONE
            } otherwise {
                nstate := cstate
            }
        }
        is(mainState.DONE) {
            nstate := mainState.IDLE
        }
    }
        
}

module top (
  input               io_start,
  input               clk,
  input               rstn
);
  localparam IDLE = 2'd0;
  localparam TX_DATA = 2'd1;
  localparam DONE = 2'd2;

  reg        [1:0]    cstate;
  reg        [1:0]    nstate;
  reg        [4:0]    cnt;

  always @(*) begin
    case(cstate)
      IDLE : begin
        if(io_start) begin
          nstate = TX_DATA;
        end else begin
          nstate = cstate;
        end
      end
      TX_DATA : begin
        if((cnt == 5'h1f)) begin
          nstate = DONE;
        end else begin
          nstate = cstate;
        end
      end
      default : begin
        nstate = IDLE;
      end
    endcase
  end

  always @(posedge clk or negedge rstn) begin
    if(!rstn) begin
      cstate <= IDLE;
      cnt <= 5'h0;
    end else begin
      if(io_start) begin
        cnt <= 5'h0;
      end else begin
        if((cstate == TX_DATA)) begin
          cnt <= (cnt + 5'h01);
        end
      end
      cstate <= nstate;
    end
  end


endmodule

全局enum

• SpinalHDL
• Verilog

class top extends Module{
    val io = new Bundle {
        val start = in Bool()
    }
    
    object mainState extends SpinalEnum {
        val IDLE,TX_DATA,DONE = newElement()
        setGlobal()
    }
    val cstate = mainState() setAsReg() init(mainState.IDLE)
    val nstate = mainState()
    
    val cnt = Reg(UInt(5 bits)) init(0)
    when(io.start) {
        cnt := 0
    } elsewhen(cstate === mainState.TX_DATA) {
        cnt := cnt + 1
    }
    
    cstate := nstate
    switch(cstate) {
        is(mainState.IDLE) {
            when(io.start) {
                nstate := mainState.TX_DATA
            } otherwise {
                nstate := cstate
            }
        }
        is(mainState.TX_DATA) {
            when(cnt === U"5'd31") {
                nstate := mainState.DONE
            } otherwise {
                nstate := cstate
            }
        }
        is(mainState.DONE) {
            nstate := mainState.IDLE
        }
    }
        
}

`define mainState_IDLE 2'b00
`define mainState_TX_DATA 2'b01
`define mainState_DONE 2'b10


module top (
  input               io_start,
  input               clk,
  input               rstn
);

  reg        [1:0]    cstate;
  reg        [1:0]    nstate;
  reg        [4:0]    cnt;

  always @(*) begin
    case(cstate)
      `mainState_IDLE : begin
        if(io_start) begin
          nstate = `mainState_TX_DATA;
        end else begin
          nstate = cstate;
        end
      end
      `mainState_TX_DATA : begin
        if((cnt == 5'h1f)) begin
          nstate = `mainState_DONE;
        end else begin
          nstate = cstate;
        end
      end
      default : begin
        nstate = `mainState_IDLE;
      end
    endcase
  end

  always @(posedge clk or negedge rstn) begin
    if(!rstn) begin
      cstate <= `mainState_IDLE;
      cnt <= 5'h0;
    end else begin
      if(io_start) begin
        cnt <= 5'h0;
      end else begin
        if((cstate == `mainState_TX_DATA)) begin
          cnt <= (cnt + 5'h01);
        end
      end
      cstate <= nstate;
    end
  end


endmodule

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本文作者： 董续胜

本文链接： https://dxsm.github.io/p/spinalhdl-enum.html

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