SpinalHDL基础-时序逻辑

Reg寄存器

• SpinalHDL
• Verilog

class top extends Module{
    //方式1
    val a = Reg(UInt(8 bits))  
    a := 3    
    
    //方式2
    val b = UInt(8 bits) setAsReg()
    b := a
}

module top (
  input               clk,
  input               rstn
);

  reg        [7:0]    a;
  reg        [7:0]    b;

  always @(posedge clk) begin
    a <= 8'h03;
    b <= a;
  end


endmodule

带复位的寄存器

• SpinalHDL
• Verilog

class top extends Module{
    //方式1
    val a = Reg(Bits(8 bits)) init(0)   
    a := 3  
    
    //方式2
    val b = RegInit(B(1,8 bits))
    b := a
    
    //方式3b
    val c = Bits(8 bits) setAsReg() init 0   
    c := b 
}

module top (
  input               clk,
  input               rstn
);

  reg        [7:0]    a;
  reg        [7:0]    b;
  reg        [7:0]    c;

  always @(posedge clk or negedge rstn) begin
    if(!rstn) begin
      a <= 8'h0;
      b <= 8'h01;
      c <= 8'h0;
    end else begin
      a <= 8'h03;
      b <= a;
      c <= b;
    end
  end


endmodule

改为上升沿复位

• SpinalHDL
• Verilog

SpinalConfig(mode = Verilog,
  defaultConfigForClockDomains = ClockDomainConfig(resetKind = ASYNC,
    clockEdge = RISING,
    resetActiveLevel = HIGH))
.generate(new top())

module top (
  input               clk,
  input               rst
);

  reg        [7:0]    a;
  reg        [7:0]    b;
  reg        [7:0]    c;

  always @(posedge clk or posedge rst) begin
    if(rst) begin
      a <= 8'h0;
      b <= 8'h01;
      c <= 8'h0;
    end else begin
      a <= 8'h03;
      b <= a;
      c <= b;
    end
  end


endmodule

寄存器打拍

• SpinalHDL
• Verilog

class top extends Module{
    val a = Reg(Bits(8 bits)) init(0)   
    a := 3  
    
    val b = RegNext(a)
    
    //带复位的打拍
    val c = RegNext(a) init(0)
    
    //带条件的打拍
    val en = Bool()
    val d = RegNextWhen(a,en && a.xorR)
}

module top (
  input               clk,
  input               rstn
);

  reg        [7:0]    a;
  reg        [7:0]    b;
  reg        [7:0]    c;
  wire                en;
  reg        [7:0]    d;

  always @(posedge clk or negedge rstn) begin
    if(!rstn) begin
      a <= 8'h0;
      c <= 8'h0;
    end else begin
      a <= 8'h03;
      c <= a;
    end
  end

  always @(posedge clk) begin
    b <= a;
    if((en && (^a))) begin
      d <= a;
    end
  end


endmodule

生活不止眼前的苟且，还有诗和远方

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本文作者： 董续胜

本文链接： https://dxsm.github.io/p/spinalhdl-sequential.html

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