SpinalHDL基础-BlackBox

外联RTL

• SpinalHDL
• Verilog

class adder(width: Int) extends BlackBox {
  addGeneric("WIDTH", width)

  val io = new Bundle {
    val ain = in UInt(width bits)
    val bin = in UInt(width bits)
    val add_out = out UInt(width bits)
  }
  noIoPrefix()

  addRTLPath("rtl/adder.v")
}

class top extends Module {
  val io = new Bundle {
    val ain = in UInt(16 bits)
    val bin = in UInt(16 bits)
    val add_out = out UInt(16 bits)
  }
  noIoPrefix()
  var adder0 = new adder(16)
  io.ain <> adder0.io.ain
  io.bin <> adder0.io.bin
  io.add_out <> adder0.io.add_out
}

module top (
  input      [15:0]   ain,
  input      [15:0]   bin,
  output     [15:0]   add_out
);

  wire       [15:0]   adder0_add_out;

  adder #(
    .WIDTH(16) 
  ) adder0 (
    .ain        (ain[15:0]             ), //i
    .bin        (bin[15:0]             ), //i
    .add_out    (adder0_add_out[15:0]  )  //o
  );
  assign add_out = adder0_add_out;

endmodule

内联RTL

• SpinalHDL
• adder.v
• top.v

class adder(width: Int) extends BlackBox {
  addGeneric("WIDTH", width)

  val io = new Bundle {
    val ain = in UInt(width bits)
    val bin = in UInt(width bits)
    val add_out = out UInt(width bits)
  }
  noIoPrefix()

  setInlineVerilog(
    """module adder #(
      |    parameter WIDTH = 16
      |) (
      |    input      [WIDTH-1:0] ain    ,
      |    input      [WIDTH-1:0] bin    ,
      |    output reg [WIDTH-1:0] add_out
      |);
      |
      |always @(*) begin
      |  add_out = ain + bin;
      |end
      |
      |endmodule
    """.stripMargin)
}

class top extends Module {
  val io = new Bundle {
    val ain = in UInt(16 bits)
    val bin = in UInt(16 bits)
    val add_out = out UInt(16 bits)
  }
  noIoPrefix()
  var adder0 = new adder(16)
  io.ain <> adder0.io.ain
  io.bin <> adder0.io.bin
  io.add_out <> adder0.io.add_out
}

module adder #(
    parameter WIDTH = 16
) (
    input      [WIDTH-1:0] ain    ,
    input      [WIDTH-1:0] bin    ,
    output reg [WIDTH-1:0] add_out
);

always @(*) begin
  add_out = ain + bin;
end

endmodule

module top (
  input      [15:0]   ain,
  input      [15:0]   bin,
  output     [15:0]   add_out
);

  wire       [15:0]   adder0_add_out;

  adder #(
    .WIDTH(16) 
  ) adder0 (
    .ain        (ain[15:0]             ), //i
    .bin        (bin[15:0]             ), //i
    .add_out    (adder0_add_out[15:0]  )  //o
  );
  assign add_out = adder0_add_out;

endmodule

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本文作者： 董续胜

本文链接： https://dxsm.github.io/p/spinalhdl-blackbox.html

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