SpinalHDL基础-数组

二位数组

• SpinalHDL
• Verilog

class top extends Module {
    val para_buf = Vec(UInt(8 bits),4)
    para_buf(0) := 1
    para_buf(1) := 2
    para_buf(2) := 3
    para_buf(3) := 4    
}

module top (
);

  wire       [7:0]    para_buf_0;
  wire       [7:0]    para_buf_1;
  wire       [7:0]    para_buf_2;
  wire       [7:0]    para_buf_3;

  assign para_buf_0 = 8'h01;
  assign para_buf_1 = 8'h02;
  assign para_buf_2 = 8'h03;
  assign para_buf_3 = 8'h04;

endmodule

三维数组

• SpinalHDL
• Verilog

class top extends Module {
    val para_buf = Vec(Vec(UInt(8 bits),4),2)
    para_buf(0)(0) := 1
    para_buf(1)(0) := 2
    para_buf(0)(1) := 3
    para_buf(1)(1) := 4
    para_buf(0)(2) := 5
    para_buf(1)(2) := 6
    para_buf(0)(3) := 7
    para_buf(1)(3) := 8
}

module top (
);

  wire       [7:0]    para_buf_0_0;
  wire       [7:0]    para_buf_0_1;
  wire       [7:0]    para_buf_0_2;
  wire       [7:0]    para_buf_0_3;
  wire       [7:0]    para_buf_1_0;
  wire       [7:0]    para_buf_1_1;
  wire       [7:0]    para_buf_1_2;
  wire       [7:0]    para_buf_1_3;

  assign para_buf_0_0 = 8'h01;
  assign para_buf_1_0 = 8'h02;
  assign para_buf_0_1 = 8'h03;
  assign para_buf_1_1 = 8'h04;
  assign para_buf_0_2 = 8'h05;
  assign para_buf_1_2 = 8'h06;
  assign para_buf_0_3 = 8'h07;
  assign para_buf_1_3 = 8'h08;

endmodule

for循环

• SpinalHDL
• Verilog

class top extends Module {
    val para_buf = Vec(UInt(8 bits),4)
    for(element <- para_buf) {
        element := 0
    }

    val data_buf = Vec(UInt(8 bits),4)
//  for(i <- 0 until data_buf.size) {
    for(i <- data_buf.indices) {  //idea建议使用indices
        data_buf(i) := i + 1
    }
}

module top (
);

  wire       [7:0]    para_buf_0;
  wire       [7:0]    para_buf_1;
  wire       [7:0]    para_buf_2;
  wire       [7:0]    para_buf_3;
  wire       [7:0]    data_buf_0;
  wire       [7:0]    data_buf_1;
  wire       [7:0]    data_buf_2;
  wire       [7:0]    data_buf_3;

  assign para_buf_0 = 8'h0;
  assign para_buf_1 = 8'h0;
  assign para_buf_2 = 8'h0;
  assign para_buf_3 = 8'h0;
  assign data_buf_0 = 8'h01;
  assign data_buf_1 = 8'h02;
  assign data_buf_2 = 8'h03;
  assign data_buf_3 = 8'h04;

endmodule

map函数

• SpinalHDL
• Verilog

class top extends Module {
    val para_buf = Vec(UInt(8 bits),4)
    para_buf.map(_ := 0)
}

module top (
);

  wire       [7:0]    para_buf_0;
  wire       [7:0]    para_buf_1;
  wire       [7:0]    para_buf_2;
  wire       [7:0]    para_buf_3;

  assign para_buf_0 = 8'h0;
  assign para_buf_1 = 8'h0;
  assign para_buf_2 = 8'h0;
  assign para_buf_3 = 8'h0;

endmodule

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本文作者： 董续胜

本文链接： https://dxsm.github.io/p/spinalhdl-array.html

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