module afifo
#(parameter DATA_WIDTH = 64,
            FIFO_DEPTH = 8,
            AF_LEVEL   = (1<<FIFO_DEPTH - 10),
            AE_LEVEL   = 10
)
(
  input                         wclk          ,
  input                         wrst          ,
  input                         wen           ,
  input       [DATA_WIDTH-1:0]  wdata         ,
  output reg                    wfull         ,
  output reg                    walmost_full  ,

  input                         rclk          ,
  input                         rrst          ,
  input                         ren           ,
  output reg  [DATA_WIDTH-1:0]  rdata         ,
  output reg                    rempty        ,
  output reg                    ralmost_empty
);


wire                  fifo_rd;
wire                  fifo_wr;
wire [FIFO_DEPTH-1:0] raddr;
wire [FIFO_DEPTH-1:0] waddr;
reg  [DATA_WIDTH-1:0] memory [0:(1<<FIFO_DEPTH)-1];

wire                  wen_mask;
wire [FIFO_DEPTH:0]   wbinnext;
wire [FIFO_DEPTH:0]   wptrnext;
reg  [FIFO_DEPTH:0]   wbin;
reg  [FIFO_DEPTH:0]   wptr;
reg  [FIFO_DEPTH:0]   wptr_rsync1;
reg  [FIFO_DEPTH:0]   wptr_rsync2;
wire [FIFO_DEPTH:0]   wbin_rsync;

wire                  ren_mask;
wire [FIFO_DEPTH:0]   rbinnext;
wire [FIFO_DEPTH:0]   rptrnext;
reg  [FIFO_DEPTH:0]   rbin;
reg  [FIFO_DEPTH:0]   rptr;
reg  [FIFO_DEPTH:0]   rptr_wsync1;
reg  [FIFO_DEPTH:0]   rptr_wsync2;
wire [FIFO_DEPTH:0]   rbin_wsync;

genvar i;

//*************************************
// Dual port RAM
//*************************************
assign fifo_wr = wen_mask;
always @(posedge wclk) begin
  if(fifo_wr)
    memory[waddr] <= wdata;
end

assign fifo_rd = ren_mask;
always @(posedge rclk) begin
  if(fifo_rd)
    rdata <= memory[raddr];
end
//

//*************************************
// sync wptr to rclk domain
//*************************************
always @(posedge rclk or negedge rrst) begin
  if(rrst)
    {wptr_rsync2,wptr_rsync1} <= 0;
  else
    {wptr_rsync2,wptr_rsync1} <= {wptr_rsync1,wptr};
end

generate
  for(i=FIFO_DEPTH;i>=0;i=i-1) begin: wbin_rsync_gen
    assign wbin_rsync[i] = ^({ {i{1'b0}},wptr_rsync2[FIFO_DEPTH:i]});
  end
endgenerate

//*************************************
// sync rptr to wclk domain
//*************************************
always @(posedge wclk or negedge wrst) begin
  if(wrst)
    {rptr_wsync2,rptr_wsync1} <= 0;
  else
    {rptr_wsync2,rptr_wsync1} <= {rptr_wsync1,rptr};
end

generate
  for(i=FIFO_DEPTH;i>=0;i=i-1) begin: rbin_wsync_gen
    assign rbin_wsync[i] = ^({ {i{1'b0}},rptr_wsync2[FIFO_DEPTH:i]});
  end
endgenerate

//*************************************
// rd addr generate
//*************************************
always @(posedge rclk or negedge rrst) begin
  if(rrst)
    {rbin,rptr} <= 0;
  else
    {rbin,rptr} <= {rbinnext,rptrnext};
end
assign raddr    = rbin[FIFO_DEPTH-1:0];
assign ren_mask = ren & (~rempty);
assign rbinnext = ren_mask ? (rbin + 1'b1) : rbin;
assign rptrnext = (rbinnext>>1) ^ rbinnext;


//*************************************
// wr addr generate
//*************************************
always @(posedge wclk or negedge wrst) begin
  if(wrst)
    {wbin,wptr} <= 0;
  else
    {wbin,wptr} <= {wbinnext,wptrnext};
end
assign waddr = wbin[FIFO_DEPTH-1:0];
assign wen_mask = (wen & (~wfull));
assign wbinnext = wen_mask ? (wbin + 1'b1) : wbin;
assign wptrnext = (wbinnext>>1) ^ wbinnext;

//*************************************
// FIFO status
//*************************************
always @(posedge rclk or negedge rrst) begin
  if(rrst)
    rempty <= 1'b1;
  else
    rempty <= (rptrnext == wptr_rsync2);
end

always @(posedge rclk or negedge rrst) begin
  if(rrst)
    ralmost_empty <= 1'b1;
  else
    ralmost_empty <= (wbin_rsync - rbinnext <= AE_LEVEL);
end

always @(posedge wclk or negedge wrst) begin
  if(wrst)
    wfull <= 0;
  else
    wfull <= (wptrnext == {~rptr_wsync2[FIFO_DEPTH:FIFO_DEPTH-1],rptr_wsync2[FIFO_DEPTH-2:0]});
end

always @(posedge wclk or negedge wrst) begin
  if(wrst)
    walmost_full <= 1'b1;
  else
    walmost_full <= (wbinnext - rbin_wsync >= AF_LEVEL);
end

endmodule

design = tb
verilog_flist = -f ./test.vc tb.v
vhd_flist =
wave = wave.fsdb

#whether to open verdi wave gui
ifdef wave
	verdi_cmd += -ssf $(wave)
endif

.PHONY: help clean ius compile verdi

help:
	@echo "#==============================================================="
	@echo "# [Info] make help    : show help infomation"   
	@echo "# [Info] make clean   : clean ius and verdi compile library,log"   
	@echo "# [Info] make compile : compile for verdi"   
	@echo "# [Info] make verdi   : raise verdi gui"   
	@echo "#==============================================================="

clean:
	@rm chip_lib.lib++ work.lib++ INCA_libs verdiLog vericomLog vhdlcomLog -rf

ius:
	irun +access+wr -smartorder -clean -ntcnotchks -V93 -vtimescale 1ns/1ps +define+RD=1 -work chip_lib $(verilog_flist) $(vhd_flist) -top $(design) -64bit

compile:
ifdef vhdl_flist
	vhdlcom -V93 -sup_sem_error -smartorder -work chip_lib $(vhdl_flist)
endif
ifdef verilog_flist
	vericom -sv +systemverilog+sv +v95ext+v95 +verilog2001ext+v -ignorekwd_config +define+RD=1  -work chip_lib $(verilog_flist)
endif

verdi:compile
	verdi -lib chip_lib $(verdi_cmd) &

[user]
  name = victor.dong
  email = dxs_uestc@163.com
[color]
  ui = auto
[alias]
  st = status
  co = checkout
  ci = commit
  br = branch
  df = diff
  dfn = diff --name-only
  dfs = diff --staged
  dft = difftool
  dfts = difftool --staged
  mr = merge
  mrt = mergetool
  last = log -1 HEAD
  amend = commit -C HEAD -a --amend
  lg = log --color --graph --pretty=format:'%C(yellow)%h%C(reset) - %C()%cd%C(reset) %C()<%an>%C(reset)%C(red)%d%C(reset) %C(ul)%s%C(reset)' --abbrev-commit --date=format:'%y/%m/%d %H:%M:%S'
  ls = log --name-only --color --graph --pretty=format:'%C(yellow)%h%C(reset) - %C()%cd%C(reset) %C()<%an>%C(reset)%C(red)%d%C(reset) %C(ul)%s%C(reset)' --abbrev-commit --date=format:'%y/%m/%d %H:%M:%S'

#not show log in new page
[core]
	pager =

#diff tool use beyond compare
[diff]
  tool = bcomp
[difftool "bcomp"]
  cmd = \"/usr/bin/bcompare\" \"$LOCAL\" \"$REMOTE\"
[difftool]
  prompt = false

#merge tool use beyond compare
[merge]
  tool = bcomp
[mergetool "bcomp"]
  cmd = \"/usr/bin/bcompare\" \"$LOCAL\" \"$REMOTE\" \"$BASE\" \"$MERGED\"
[mergetool]
  prompt = false

initial begin  //verilog internal signal access
  force xxx.xxx.xxx = 16'hfffd;
  #500 release xxx.xxx.xxx;
end

initial begin //vhdl internal signal access
  $nc_force("xxx.xxx.xxx", "X'FFFD'");
  #500 $nc_release(xxx.xxx.xxx);
end

//mul.v
module mul(
  input             clk,
  input             rst_n,
  input             in_vld,
  input      [11:0] mul_ain,
  input      [11:0] mul_bin,
  output reg [22:0] mul_out,
  output reg        out_vld
);

always @(posedge clk)
  if(in_vld)
    mul_out <= $signed(mul_ain) * $signed(mul_bin);

always @(posedge clk,negedge rst_n)
  if(!rst_n)
    out_vld <= 1'b0;
  else
    out_vld <= in_vld;

endmodule

module test_func();

int arr[];

//************************************
// operator = "+", return a.sum
// operator = "x", return a.product
//************************************
function automatic int alu(
    const ref int a[],           //数组引用,const不能改变数组
    input string operator = "+"  //指定default值
);

int result;

if(operator=="x") begin
  result = 1;
  for(a[i])
    result *= a[i];
end
else begin
  result = 0;
  for(a[i])
    result += a[i];
end

return result;
endfunction

initial begin
  arr = new[5];
  arr = '{1,2,3,4,5};
  $display(alu(arr));    //15, use default operator
  $display(alu(arr,"x")) //120
end

endmodule